CV
Biography
I am a Full Professor at the School of Control and Computer Engineering, North China Electric Power University (NCEPU). Prior to this, I was an Associate Professor at the State Key Laboratory of Processors (SKLP), Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) from 2018 to 2026. I was a Research Fellow at the National University of Singapore from 2016 to 2018, and received my Ph.D. from The University of Hong Kong in 2016.
My research focuses on reconfigurable and reliable architectures for AI computing systems, with emphasis on large-scale spatial architectures, domain-specific accelerators, and hardware–software co-design. More recently my work has extended to LLM-driven hardware design automation, including hardware code generation, code-generation agents, and automated SoC design. I have published around 100 papers in leading international conferences and journals, and received Best Paper Awards at GLSVLSI 2021 and IEEE Transactions on Computers 2021, the CAS Outstanding Award for Technological Achievements Transformation (2019), and the Huawei Olympus Pioneering Award (2023).
Education & Appointments
- Professor, School of Control and Computer Engineering, North China Electric Power University — 2026.06 – present
- Associate Professor, State Key Laboratory of Processors (SKLP), Institute of Computing Technology, CAS — 2018.06 – 2026.05
- Research Fellow, School of Computing, National University of Singapore — 2016.12 – 2018.06
- Ph.D. in Computer Engineering, The University of Hong Kong — 2011.09 – 2016.11
- M.E. in Electronic Engineering, Harbin Institute of Technology — 2007.09 – 2009.07
- B.E. in Electronic Engineering, Harbin Institute of Technology — 2003.09 – 2007.07
Academic Service
- Area Chair, ICML 2027 and ICLR 2027
- Associate Editor, IEEE Transactions on Emerging Topics in Computing (TETC) — 2024 – present
- Review Board Member, IEEE Transactions on Parallel and Distributed Systems (TPDS) — 2025 – present
- Technical Program Committee (TPC): DFT, FPT, CFTC, ATS, DFTS (2022–2023); FPT, DFTS, DAC (2025)
- Registration Chair, ATS 2023
- Reviewer: NeurIPS, ICML, ICLR, AAAI (since 2023); TCAD, TVLSI, TC, TPDS, TECS, TRETS (since 2018)
- Senior Member of IEEE and CCF; Member of ACM
Research Grants
As Principal Investigator
- Fault-Tolerant Chip Design under the Approximate Computing Paradigm — NSFC General Program, ¥550,000, 2027 – 2030
- Cross-Layer Processor Optimization Infrastructures — CAS Strategic Priority Program (Class B), ¥10,740,000, 2024 – 2028
- Representation and Application of Multimodal IC Data — CAS Computing Power Program, ¥710,000, 2025 – 2026
- Reliability Evaluation of Remote Sensing Systems — CASC, ¥500,000, 2024
- Computational Storage Based Big Data Processing — MIP, ¥1,300,000, 2023 – 2024
- Resilient AI Tool Chain for COTS Devices — CASC, ¥300,000, 2023
- Elastic Fault-Tolerant DLA Architecture — NSFC General Program, ¥570,000, 2022 – 2025
- Energy-Efficient Graph Processing Acceleration on FPGAs — NSFC Young Scientists Program, ¥270,000, 2020 – 2022
- Automatic DLA Hardening — SKLCA, ¥300,000, 2021 – 2022
As Co-Principal Investigator / Participant
- Cross-Layer Chip DSE Methods — National Key R&D Program (sub-project), ¥1,600,000, 2023 – 2025
- Micro-storage Based Computational Storage — Huawei, ¥1,200,000, 2023 – 2024
- Open AIoT Processor Architecture Design — CAS, ¥12,000,000, 2020 – 2021
- Computation Storage Based Stream Processing — Huawei, ¥1,200,000, 2020 – 2021
Publications
See the Publications page for the complete list.
Contact
School of Control and Computer Engineering, North China Electric Power University No.2 Beinong Road, Changping District, Beijing 102206, China Email: liucheng@ncepu.edu.cn